Advanced Microelectronics 1. Ladies and Gentlemen, Good Afternoon and thank you for lasting this long. I know that it has been a long day full of briefings....and this is yet another one....but at least this is the LAST one before tonight's evening social event! So, I will try to be merciful here. I would like to tell you about the Advanced Microelectronics Program which, like everything else in the Department of Defense, goes by its acronym...A.M.E. Now DARPA has long been at the forefront of semiconductor technology development, with a history of amazing results across many programs. The technologies being developed in the AME Program are now themselves at a very exciting point--moving from basic processes and devices, toward combinations of devices, then ultimately toward integrated circuits. 2. This is the obligatory briefing outline....hopefully, the flow of the talk since the sequencing of the slides has been set in advance. First - an overview to give some perspective on our goals and expected impacts. Then - our first results on very small transistors -- recently collected and hot off the press. Now when I say "small transistors" what I mean are things with dimensions of about 25 nanometers -- that's about 200 times smaller than the thickness of human hair! That is actually pretty small when you think about it! After that, I will describe the research efforts to exploit the 3rd dimension -- that is the space above the usual plane of active devices. I will talk first about vertical transistors which can provide greater levels of functionality per active circuit area -- things like an entire static RAM cell in a single pillar of silicon. I will talk then about another way to exploit the 3rd dimension -- by actually placing active transistors in many layers -- something like a layer cake with lots of layers of cake and icing. The AME version will not taste as good as the cake, but it will provide highly capable compact electronic processing and memory. Finally, I will introduce the direction of the program -- and here is where we are looking for help -- we are pushing the devices and integration technologies toward complex structures and circuit level validations. We need some stressing circuit applications for AME -- and if you have any great ideas, please contact me. 3. The conventional approach to semiconductor processing results in a 2 dimensional planar world of transistors. We are pushing forward to transition from the 2D planar integrated circuit technologies of today to a truly 3-dimensional device and interconnect technology. This is the AME dream. The keys to realizing it are clear -- the combination of creating very small transistors on multiple layers with low-loss interconnects and the creation of new devices -- more complex then the simple transistor -- but able to provide greater functionality per unit area (or volume). This is the AME dream. 4. Two pictures here. I think that you will have to take my word for it but...On the left side you see today's state-of-the-art microprocessor -- the transistors have critical dimensions of about 250nm -- the circuit can run at speeds up to about 600MHz and there are about 10 million transistors in a piece of silicon the size of a postage stamp. Under AME, we are developing 25nm devices -- a reduction of about 10x.from today. The picture on the right -- the one that is mostly blue with a small square dot in the center -- that dot is the microprocessor done with AME technologies. The rest of the space could be filled up with a few billion more transistors to make an extremely capable processor or a very dense memory. 5. Two pictures here. I think that you will have to take my word for it, but...On the left side you see today's state-of-the-art microprocessor -- the transistors have critical dimensions of about 250nm - the circuit can run at speeds up to about 600MHz and there are about 10 million transistors in a piece of silicon the size of a postage stamp. Under AME, we are developing 25nm devices - a reduction of about 10x.from today. The picture on the right - the one that is mostly blue with a small square dot in the center - that dot is the microprocessor done with AME technologies. The rest of the space could be filled up with a few billion more transistors to make an extremely capable processor or a very dense memory. 6. Next, the gate electrode is deposited into that 25nm slot and the transistor's source and drain regions created. The final structure is shown graphically on the left of this chart. We are making more than one major departure from today's techniques with these devices - we are using Titanium-Nitride rather than polysilicon as the gate material. This provides us with a degree of freedom to use the conductor's workfunction to set the turn-on voltage of the transistor. The qualities of the oxide and the gate are critical in setting the transistors electrical performance - from its transconductance (gain) to its current drive, threshold voltage, and the simple fact that the thing really turns on and off under gate control. On the right side you will see a cross-section of a finished 25nm transistor. We have built them and we have tested them and collected current-voltage data - and they really work! They show transistor action however these devices are not without problems - usually called short-channel effects. 7. There are ways to overcome these short channel effects. A double-gate transistor is one approach, but the gates must be completely aligned to each other. If the gates are not exactly aligned, then the major advantages are lost. The double gated transistor is a simple device concept, but it turns out to be an extreme challenge to realize this device from a processing/fabrication standpoint. 8. Under the AME program, researchers from UC-Berkeley have demonstrated the first reliably fabricatable double-gated transistor with dimensions of 30nm - and below. The innovations are in the large contact area for good ohmic contacts and the ability to employ multiple channel fingers - those little yellow rectangles there on the chart that is hopefully displayed behind me. The more fingers - the more current delivered. 9. On the left side you will see a 30nm device with 2 parallel channels - those of us immersed in the technology refer to them as those faint grayish things you can barely see between the big grayish rectangles. The UC Berkeley team has successfully used this approach in fabricating transistors down to about 18nm. The resulting transistors have yielded excellent results - good transconductance, good current drive, and the device turns off when told to so by a zero voltage on the gate. 10. Departing from the 2 dimensional world of the single and double gated transistor, the AME program is researching approaches to provide greater circuit functionality per unit area - mainly we seek to exploit the vertical direction. Left side of this chart shows a conventional field effect transistor, except that it is oriented vertically and is created using series of deposition and etch steps that are somewhat decoupled from lithography - which is a good thing when trying to make 25nm features. In addition, using deposition to grow the transistor might allow us to place specially engineered semiconductor materials at precise locations within the device. Right hand side shows a vertical device - source on top drain on bottom, and a channel with 3 regions of this special semiconductor. The number and placement of these regions can have a huge effect on the device performance. Vertical devices open up new avenues for channel/device engineering, providing devices with greater integrated functionality per unit area - like an SRAM in a pillar of silicon. 11. A multi-layer vertical device was fabricated and indeed forms essentially a self- contained SRAM cell within the pillar. This can be 6 to 10 times less than the area used in the conventional planar device approach. Left side is an oscillscope trace of the switching characteristics of the SRAM. As you can clearly see (or take my word for it) the pillar is functioning as an SRAM latch. 12. Up to today, the delays associated with a circuit have been dominated by the delays in passing a signal through the transistors. In the future, as devices will get smaller and faster, while the interconnect wires will get smaller but slower due to resistance and parasitics. At some point probably not too far off, interconnect delays may dominate. There are fundamental challenges in providing room-temperature solutions here - several approaches are being pursued within DARPA - including photonics and wireless. And there are approaches involving 3D integration architectures that have the potential to have a high payoff. 13. For example, the interconnects between devices might be kept very short if we had the ability to place transistors on multiple layers - the concept shown graphically here. There are actually a few approaches to realizing 3-dimensional circuits - which I will quickly go through. 14. First, epitaxial lateral overgrowth of silicon can be used to precisely grow single crystal layers from seed layers below. Individual transistors could then be created in these layers for fully 3D circuits. This type of process is attractive because if can grow single crystal layers that have the necessary crystallographic orientation. We have research at Purdue and Stanford which has demonstrated three layers of silicon separated by insulators. 15. Here is where we could use some of your help. In the end, what we want is more than devices - we want to realize a function or hopefully a set of functions. Given the extremely small transistors and the possibility of 3D integration, we are studying what circuits would benefit most from AME technologies. For example, each pixel or set of pixels of an imager or array sensor could have its own signal processor and memory. We have also studied the implementation of the FFT and programmable logic - but we could really use your suggestions of applications. 16. We are moving forward from device technologies toward integration and interconnection. Design rules are being established for the demonstration process at MIT Lincoln Labs. We are ready for your circuit application ideas. 17. We are moving forward from device technologies toward integration and interconnection. Design rules are being established for the demonstration process at MIT Lincoln Labs. We are ready for your circuit application ideas.